The present invention relates to a semiconductor memory and, more specifically, to a high-speed circuit of a synchronous burst memory capable of performing an address pipeline operation, which is applied to a synchronous pipelined burst static random access memory (PBSRAM) and cache-mounted dynamic random access memory (DRAM).
In a prior art PBSRAM, an address is decoded in synchronization with a clock signal in read mode, a very small potential is read out of a memory cell selected by the decoded address and amplified through a sense amplifier, and data of the sense amplifier is transferred to an output register.
Addresses are generated in sequence based on an input address using a given method such as a linear method and an interleaving method. A series of data items (e.g., four data items) read out from a memory cell corresponding to a series of addresses is output from an output register.
The PBSRAM has the feature that the first access time period of the first access required until the first data read out of a memory cell of the first-designated address is output is longer than the second to fourth access time periods of the second to fourth accesses required until the second to fourth data read out of memory cells of the second address et seq.
FIG. 1 shows an example of timing of the prior art PBSRAM in read mode.
As shown in FIG. 1, the second to fourth access time periods each correspond to two clocks necessary for outputting data from the output register, whereas the first access time period requires extra time corresponding to clocks (the number of which is .alpha.) necessary for decoding an address, amplifying a very small potential read out of a selected memory cell by the sense amplifier, and transferring data to the output register.
The number of clocks necessary for satisfying the first access is referred to as read latency. In the prior art PBSRAM, the read latency is long. Since the read latency is expressed by 2 clocks+.alpha., it is 4 when .alpha. is 2.
The above-described prior art synchronous burst memory capable of performing an address pipeline operation cannot be increased in speed since the read latency is long.